Sunday, 21 December 2014

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PIC stands for Peripheral Interface Controller given by Microchip Technology to identify its single-chip micro controllers. These devices have been very successful in 8-bit micro controllers. The main reason is that Microchip Technology has continuously upgraded the device architecture and added needed peripherals to the micro controller to suit customers' requirements. The development tools such as assembler and simulator are freely available on the internet at 
The architectures of various PIC micro controllers can be divided as follows.

Low - end PIC Architectures 

Microchip PIC microcontrollers are available in various types. When PIC microcontroller MCU was first available from General Instruments in early 1980's, the microcontroller consisted of a simple processor executing 12-bit wide instructions with basic I/O functions. These devices are known as low-end architectures. They have limited program memory and are meant for applications requiring simple interface functions and small program & data memories. Some of the low-end device numbers are

Mid range PIC Architectures

Mid range PIC architectures are built by upgrading low-end architectures with more number of peripherals, more number of registers and more data/program memory. Some of the mid-range devices are
Program memory type is indicated by an alphabet.
F = Flash
RC = Mask ROM
Popularity of the PIC microcontrollers is due to the following factors.
  1. Speed: Harvard Architecture, RISC architecture, 1 instruction cycle = 4 clock cycles.
  2. Instruction set simplicity: The instruction set consists of just 35 instructions (as opposed to 111 instructions for 8051).
    1. Power-on-reset and brown-out reset. Brown-out-reset means when the power supply goes below a specified voltage (say 4V), it causes PIC to reset; hence malfunction is avoided.
      A watch dog timer (user programmable) resets the processor if the software/program ever malfunctions and deviates  from its normal operation.
    2. PIC microcontroller has four optional clock sources.
      •   Low power crystal
      •   Mid range crystal
      •   High range crystal
      •   RC oscillator (low cost).
    3. Programmable timers and on-chip ADC.
    4. Up to 12 independent interrupt sources.
    5. Powerful output pin control (25 mA (max.) current sourcing capability per pin.)
    6. EPROM/OTP/ROM/Flash memory option.
    7. I/O port expansion capability.

CPU Architecture

The CPU uses Harvard architecture with separate Program and Variable (data) memory interface. This facilitates instruction fetch and the operation on data/accessing of variables simultaneously.
Fig 1

PIC Memory Organisation

PIC microcontroller has 13 bits of program memory address. Hence it can address up to 8k of program memory. The program counter is 13-bit. PIC 16C6X or 16C7X program memory is 2k or 4k. While addressing 2k of program memory, only 11-  bits are required. Hence two most significant bits of the program counter are ignored. Similarly, while addressing 4k of memory, 12 bits are required. Hence the MSb of the program counter is ignored.

Fig 2

The program memory map of PIC16C74A is shown in Fig 2 
On reset, the program counter is cleared and the program starts at 00H. Here a 'goto' instruction is required that takes the processor to the mainline program.
When a peripheral interrupt, that is enabled, is received, the processor goes to 004H. A suitable branching to the interrupt service routine (ISR) is written at 004H.

Data memory (Register Files)

Data Memory is also known as Register File. Register File consists of two components.
  1. General purpose register file (same as RAM).
     2. Special purpose register file (similar to SFR in 8051).
Fig 3
The special purpose register file consists of input/output ports and control registers. Addressing from 00H to FFH requires 8 bits of address. However, the instructions that use direct addressing modes in PIC to address these register files use 7 bits of instruction only. Therefore the register bank select (RP0) bit in the STATUS register is used to select one of the register banks.
In indirect addressing FSR register is used as a pointer to anywhere from 00H to FFH in the data memory.
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